With the recent improvement and multiplication in function of a semiconductor device, the WL-CSP (Wafer Level-Chip Scale Package) technique has been increasingly practicalized. According to the WL-CSP technique, the packaging step is completed in a wafer state, and the size of each chip cut out from the wafer by dicing is the package size.
A semiconductor device to which the WL-CSP technique is applied includes a semiconductor chip 92 whose surface is entirely covered with a passivation film 91, a polyimide layer 93 stacked on the passivation film 91, rewiring 94 formed on the polyimide layer 93, a sealing resin layer 95 stacked on the polyimide layer 93 and the rewiring 94 and a solder ball 96 arranged on the sealing resin layer 95, as shown in FIG. 13. The passivation film 91 is provided with a pad opening 98 for exposing a part of the internal wiring as an electrode pad 97. The rewiring 94 is connected to the electrode pad 97 through a through-hole 99 penetratingly formed in the polyimide layer 93. Further, the rewiring 94 is connected with the solder ball 96 through a post 100 penetrating the sealing resin layer 95. In this semiconductor device, the solder ball 96 is connected to a pad provided on a mounting board, thereby attaining mounting on the mounting board (electrical and mechanical connection to the mounting board).
In the process of manufacturing such a semiconductor device, a wafer provided with a plurality of semiconductor chips is prepared. In this wafer state, the polyimide layer 93 and the rewiring 94 are first formed on the passivation film 91 covering the surface of the wafer. Then, the post 100 is formed on a predetermined position of the rewiring 94 by a method such as plating. Thereafter epoxy resin employed as the material for the sealing resin layer 95 is supplied to the surface of the wafer for embedding the post 100 therein. After the epoxy resin is cured, the surface of the epoxy resin is ground with a grinder, and the surface (tip end surface) of the post 100 is exposed from the epoxy resin.
However, a metallic material such as copper forming the post 100 has ductility, whereby the tip end of the post 100 extends and spreads (sags) on the surface of the epoxy resin (sealing resin layer 95) due to the grinder at the time of grinding the epoxy resin, as shown by a phantom line in FIG. 13. Such sagging of the metallic material may cause a problem such as a short circuit between a plurality of posts 100, for example.
After the epoxy resin is ground with the grinder, therefore, an ammonia-based etching solution is supplied to the surface of the wafer, and etching is performed for removing the metallic material extending and spreading on the surface of the epoxy resin. After this etching, the solder ball 96 is formed on the post 100. Then, the wafer is cut (diced) along dicing lines set between the adjacent semiconductor chips in the wafer. Thus, the semiconductor device having the structure shown in FIG. 13 is obtained.
After the etching, the position of the tip end surface of the post 100 is lower by one step than the position of the surface of the sealing resin layer 95, as shown in FIG. 13. Therefore, a corner 90 formed by the surface of the sealing resin layer 95 and another surface (inner surface of a through-hole receiving the post 100) of the sealing resin layer 95 in contact with the side surface of the post 100 comes into contact with the proximal end of the solder ball 96 formed on the post 100. If this corner 90 is in contact with the solder ball 96, stress may concentrate on the contact portion between the corner 90 and the solder ball 96 when the semiconductor chip 92 or the mounting board undergoes thermal expansion/shrinkage or the like, thereby causing a damage such as cracking in the solder ball 96.
FIG. 14 is a sectional view showing another structure of a semiconductor device to which the WL-CSP technique is applied.
This semiconductor device includes a semiconductor chip 101. The entire surface of the semiconductor chip 101 is covered with a passivation film 102. This passivation film 102 is provided with pad openings 104 for exposing pads 103.
A polyimide layer 105 is stacked on the passivation film 102. Rewirings 106 are formed on the polyimide layer 105. These rewirings 106 are connected to the pads 103 through through-holes 107 penetratingly formed in the polyimide layer 105.
On the other hand, a first wiring layer 109, a first interlayer film 110, a second wiring layer 111 and a second interlayer film 112 are stacked under the passivation film 102 successively from the side closer to a semiconductor substrate 108 serving as the base of the semiconductor chip 101. The first wiring layer 109 and the second wiring layer 111 are electrically connected with each other through via holes 113 formed in the first interlayer film 110. The second wiring layer 111 and the pads 103 are electrically connected with each other through via holes 114 formed in the second interlayer film 112.
A sealing resin layer 115 made of epoxy resin is stacked on the polyimide layer 105 and the rewirings 106. The rewirings 106 are connected to solder balls 117 arranged on the surface of the sealing resin layer 115 through posts 116 penetrating the sealing resin layer 115.
In this semiconductor device of such a multilevel interconnection structure, the side surfaces of the semiconductor chip 101, the passivation film 102, the first interlayer film 110, the second interlayer film 112 and the sealing resin layer 115 are flush with one another and exposed. When stress is applied to the side surface of the semiconductor device, therefore, cracking (separation of the passivation film 102, the first interlayer film 110 and the second interlayer film 112) between each of the passivation film 102, the first interlayer film 110 and the second interlayer film 112 and the underlayer thereof takes place on the side surface. If such cracking progresses up to an element forming region of the semiconductor chip 101, a malfunction of a functional element formed on the element forming region may be caused.    Patent Document 1: Japanese Unexamined Patent Publication No. 2001-210760    Patent Document 2: Japanese Unexamined Patent Publication No. 2001-298120